7. Clock Signals

7.1 System Interface Clock and Internal Processor Clock Domains

In high performance systems, PECL-level differential clocks are routinely used to minimize system clock skews. The R10000 processor receives differential system clock signals at the SysClk and SysClk* pins; two additional pins, SysClkRet and SysClkRet*, are the return paths for termination of these signals.

SysClk and SysClk* are used to drive an on-chip phase-locked loop (PLL), which multiplies the system clock to create an internal processor clock, PClk.

The R10000 processor always communicates with the system at the SysClk frequency, and PClk always runs at a frequency-multiple of SysClk, according to the following formula:

PClk = SysClk*(SysClkDiv+1)/2

For example, in a 50 MHz system with SysClkDiv = 7 and SCClkDiv=2,
PClk= 50*8/2 = 200 MHz.

NOTE: It is preferred that the R10000 processor uses a differential PECL clock input. However, in a less-aggressive system, a CMOS/TTL single-ended clock can be used to drive the processor, provided its complementary clock input, SysClk*, is tied to an appropriate reference voltage (1.4V for TTL, Vcc/2 for CMOS). In any case, the reference voltage applied to SysClk* should not be less than 1.2V.

Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96

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